1. Field of the Invention:
This invention relates to the field of integrated circuits and more particularly, to the calibration and testing of integrated circuits.
2. Art Background:
Most integrated circuits are manufactured on silicon wafers, with a large number of the circuits fabricated on each wafer. Each integrated circuit is comprised of a plurality of semi-conductor devices, and is referred to as a "chip". Unfortunately, the manufacture of semi-conductor devices is not an exact science. In order for a particular integrated circuit chip to be marketable, it must perform within certain technical specifications. One of the most important performance criteria is the speed at which the chip operates. The "speed" of an integrated circuit may generally be defined as the maximum clock rate at which the integrated circuit will function properly. It is not uncommon in the semiconductor industry to have successful manufacturing yields of only 6-9% for all the chips fabricated on a wafer. Therefore, each chip must be tested prior to being sold.
Previously, quality control procedures for integrated circuits required that each chip be rigorously tested to determine if it was able to perform the functions for which it was designed. This is often a complex procedure that entails the used of special testing devices. Each chip has a unique design, therefore, the test equipment must be reconfigured each time a new circuit is tested.
It is desirable to provide a circuit design within a semi-conductor chip which permits a quick determination of the speed of the chip to assist in testing manufactured parts prior to installation in systems. The speed of different integrated circuits often vary from chip to chip on a given wafer. The speed of an integrated circuit may also vary with environmental parameters, such as power supply voltage, temperature, etc. However, it has been found that the speed at which integrated circuits operate does not vary appreciably over the surface of the chip. It is therefore possible to provide each chip with a small, self-contained circuit. This circuit, referred to in this Specification as a "speed circuit", can be used to calculate the speed at which the chip operates.
The speed circuit of the present invention reduces the cost of testing chips by obviating the need for special test equipment, and identifying chips that clearly do not meet the required standards for speed. Instead of configuring new test equipment each time a different type of chip is tested, standardized equipment can be used to test the chip by use of the speed circuit. Once acceptable chips are found, they can be further tested using other methods, if necessary. However, since most of the unmarketable chips will have been identified, the cost of testing will be greatly reduced.